1. Field of the Invention
The present invention relates to a nonvolatile memory cell, a method of programming the same and non volatile memory array and more particularly to the nonvolatile memory cell enabling low voltage programming and/or high speed programming, a method of programming same and nonvolatile memory array.
2. Description of the Related Art
A MNOS memory is one of typical semiconductor memories wherein carrier charge is stored in a gate insulator to have information nonvolatilely stored. The MNOS memory is of a laminated structure comprising a conductive gate (M), a silicon nitride film (N), a tunnel oxide film (O) and a semiconductor wherein the carrier (electron or hole) is captured at a trapping level in the silicon nitride film to store the carrier charge. In this step, the silicon nitride film of the MNOS memory was required to be more than 19 nm in thickness since the charge trapping efficiency depended on the carrier capture distance in the silicon nitride film as described in F. L. Hampton and J. R. Cricchi xe2x80x9cSpace Charge Distribution Limitation of Scale Down of MNOS Devicesxe2x80x9d, 1979 IEDM Technical Digest, p. 374. To program (write or erase) the MNOS memory, at least more than 10V or about 20V as a normal value of programming voltage was required for a electric field to be fed to a semiconductor surface via the silicon nitride film so that a carrier may be injected in the nitride film through (via a tunnel) the tunnel oxide film.
A MONOS memory is disclosed as the nonvolatile memory capable of reducing the programming voltage by E. Suzuki, H. Hiraishi, K. Ishii and Y. Hayashi, xe2x80x9cA Low-Voltage Alterable EEPROM with Metal-Oxide-nitride-Oxide and semiconductor (MONOS) Structuresxe2x80x9d, in IEEE Transaction on Electron Devices, Vol. ED-30, February 1983, p. 122). This MONOS memory is of a laminated structure comprising a conductive gate (M), a top oxide film (O), a silicon nitride film (N), a tunnel oxide film (O) and semiconductor. This structure has enabled the MONOS memory to stop hopping via the carrier trapping level in the silicon nitride film due to a potential barrier formed between the nitride film and the top oxide film, which resulted in making the nitride film as thin as possible. Further, carrier traps newly generated at the interface between the top oxide film and nitride film has enlarged a memory window to the extent it is possible to identify the stored information even if the entire insulator thickness is made thinner. This MONOS memory has made it possible to reduce the programming voltage down to 9V with the usable programming speed (0.1 msec) under the condition that the stored information is maintained for ten years as indicated in T. Nozaki, T. Tanaka, Y. Kijiya, E. Kinoshita, T. Tsuchiya and Y. Hayashi, xe2x80x9cA1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Applicationxe2x80x9d, IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April, 1991, p.497).
It has yet to be disclosed, however, whether or not it is possible to reduce programming voltage to be less than 9V under the condition that the programming speed is less than 0.1 msec and memory retention characteristics is maintained. To achieve the programming voltage of less than 9V, either programming speed or memory storage characteristics or both were required to be sacrificed. On the other hand, PAC (perpendicularly accelerated channel) injection is disclosed as a method to improve the injection efficiency to the gate insulator with the programming voltage being lowered as seen in M. Kamiya, Y. Kojima, Y. Kato, K. Tanaka and Y, Hayashi, xe2x80x9cEEPROM with High Gate Injection Efficiencyxe2x80x9d, 1982 IEDM technical Digest, 30.4, p741.
To achieve the PAC injection, a first conductive gate is disposed on a channel forming region at the source side via a gate insulator and a floating gate, on the channel forming region at the drain side. A carrier supplied from the source side to a surface of the channel forming region is once pushed from the surface to inside of the channel forming region at a drain side end portion of the first conductive gate and again drawn to the channel forming region under the floating gate. In this step, part of the carrier drawn thereto is injected in the floating gate getting over a potential barrier between the gate insulator and channel forming region surface. To have the carrier injected therein, it is required that the potential difference between the channel forming region and drain region be more than the height of the potential barrier (VB) (The potential from the outside is VBxe2x88x922xcfx86F2; 2xcfx86F2 is a Fermi-level in the channel forming region).
It has recently been found that the critical film thickness of the gate insulator under the floating gate is 8 nm. xe2x80x9cThinning a tunnel oxide film reaches its limit at 8 nm . . . Limit to a large capacity flush memoryxe2x80x9d by S. Lai, disclosed at page 70 in xe2x80x9cNikkei Microdevicexe2x80x9d published in April, 1967. The carrier injection is achieved in such a step that a control gate (or a drain gate in stead of a control gate) is capacitance-coupled with the floating gate via the insulator to control the floating gate potential, but the equivalent insulator thickness measured from the control gate becomes about twice that of the critical value. Accordingly, the control gate voltage during the programming is limited by the equivalent film thickness causing a limit to making the programming voltage lower.
Compared to the MNOS memory, the MONOS memory has achieved to some extents low voltage programming, but has problems to be resolved in terms of further reducing the programming time and realizing the lower voltage programming.
It is a purpose of the present invention to provide a nonvolatile memory cell capable of programming not onlyat a higher speed and with lower voltage compared to a MNOS memory but also with lower voltage compared to a conventional floating gate memory; and a method of programming the same and a high density nonvolatile memory array.
To achieve the purpose as described, the present invention is provided with the means featured below.
(1) A pair of source and drain regions formed in a main surface of a substrate and separated by channel forming regions therebetween; a first gate insulator formed on a surface of a first channel forming region adjacent to the source region out of the channel forming regions; a second gate insulator formed on a surface of a second channel forming region adjacent to the drain region out of the channel forming regions; a first gate electrode formed on the first gate insulator; and a second gate electrode formed on the second gate insulator, wherein the second insulator includes a first layer forming a potential barrier at the interface with the channel forming region; a third layer forming the potential barrier at the interface with the second gate electrode and the second layer forming the carrier trapping level at least a location out of the interfaces between the second layer and the first layer or the third layer and a location in the second film itself.
(2). A first potential feeding means which feeds to the drain region the first potential to supply to the carrier such energy as the carrier is capable of getting over the potential barrier formed between the second channel forming region and first layer of the second gate insulator; and a second potential feeding means which feeds to the second gate electrode a potential to form an auxiliary electric field capable of having the carrier having overcome the potential barrier reached the second layer of the second gate insulator.
(3) A pair of source and drain regions formed in a main surface of a substrate and separated therebetween by channel forming semiconductor regions in said main surface of said substrate; a second gate insulator at one side formed on a surface of a second channel forming region at one side adjacent to the source and drain region at one side out of the channel forming regions; a second gate insulator at the other side formed on a surface of a second channel forming region adjacent to the source and drain region at the other side out of the channel forming regions; a first gate insulator formed on a surface of a first channel forming region between each of the second channel forming regions; a second gate electrode at one side on the second gate insulator at one side; a second gate electrode at the other side on the gate insulator at the other side and a first gate electrode formed on the first gate insulation film, wherein the second gate insulators at one and the other sides are provided with a carrier charge trapping means. The carrier charge trapping means is fully demonstrated by a carrier trapping level formed in the gate insulator or in a layer and/or at the interface of each layer if the gate insulator is of a multi-layered structure and by conductive particulate formed from silicon and metal, etc. embedded in the gate insulator.
(4) The carrier injection from the second channel forming region to the second gate insulator is carried out by applying the predetermined potential to the drain region and second gate electrode respectively so that the energy to get over a potential barrier formed between the first layer of the second gate insulator and the second channel forming region may be applied to the carrier. Furthermore, the carrier extraction from the second gate insulator is conducted by applying to the second gate a potential whose polarity is the same as that applied when injecting the carrier therein so that electric field enabling the carrier to conduct tunnel-transition through a potential barrier layer formed between the second layer and the third layer of second gate insulating layer may be applied to the third layer.
According to the feature as described in (1) above, the carrier injected in the channel forming region from the source region is accelerated by the potential fed to the drain region and provided with so energy as to get over the potential barrier formed at the interface with the second gate insulator, thereby being injected in the second gate insulator. The injection into the second gate insulator is of high efficiency if the energy is given within the distance several (less than about 6) times of Lo in the second channel forming region, where Lo denotes a mean free path of a hot carrier. This is realized making the length of the second channel forming region shorter than 6 times of Lo. If the energy as described above is found to be insufficient for conducting the carrier injection, the gate potential applied to the second gate electrode is provided as an auxiliary means to attract the carrier to the second layer of the second gate insulator by the electric field generated thereby and capture the carrier. Part of the injected carriers are forwarded to the second gate side, but tunneling thereof to the second gate electrode of the carrier is stopped by the potential barrier between the second layer and third layer of the second gate insulator. It is, therefore, possible to capture the sufficient carriers even if the thickness of the second layer of the second gate insulator is formed thinner than the conventional one and eventually, to make the second insulator thin as a whole even if the third layer is added thereto. This enables reduction of the applied voltage to the second gate electrode when performing the carrier injection.
To inject a carrier in the second gate insulator, a carrier is first injected in the first channel forming region from the source region, according to the feature as described in (2) above. This carrier injection is achieved by forward-biasing the source region to the first channel forming region, or by feeding the potential exceeding the threshold voltage to the first gate electrode to induce a channel in the surface of the first channel forming region. Next, the predetermined potential is fed from the first potential feeding means to the drain region so that such energy as to get over the potential barrier formed at the interface between the second channel forming region and second gate insulator may be applied to the carrier. Furthermore, the predetermined potential is fed from the second potential feeding means to the second gate electrode so that an auxiliary electric field to have the carrier having overcome the potential barrier reached the second layer may be generated. To inject a carrier from the second channel forming region in one side in the second gate insulator in one side in the structure described in (3), a carrier is supplied first from the source and drain region at the other side to a channel formed in the second channel forming region at the other side, then supplied through said channel to a channel formed in the first channel forming region and then through the channel supplied to said second channel forming region in one side. Above mentioned each channel is induced in the respective channel forming region by applying to the second gate at the other side and first gate a respective potential larger than a gate threshold voltage of the respective gate.
According to the feature as described in (3) above, the stored data are independently held by the second gate insulator at one side and second gate insulator at the other side. It is, therefore, possible to store two-bit data in one.memory cell and eventually, to provide a high integration density memory.
According to the feature as described in (4) above, it is possible to inject and extract the carrier to and from the second gate insulator by applying to any of second gate electrodes the potential whose polarity is the same both in the injection and extraction. This simplifies the circuit configuration and manufacturing process for a carrier injection and extracting.